Features | Benefits |
| Pattern Generation and Error Analysis, highspeed BER Measurements up to 28.6 Gb/sec. | The combination of impairment modulation, signal generation and analysis in one instrument enables receiver BER compliance testing for today's 3rd Generation Serial and 100G standards like; IEEE802.3ba, OIF-CEI and 32GFC communications standards. |
| Integrated Stress Generator for stressed eye sensitivity (SRS) and jitter tolerance compliance testing. | A test signal's data rate, applied stress, and data pattern can be changed on the fly, independent of each other; enabling a diverse set of signal variations for testing chipset/system sensitivity. |
| Integrated, BER correlated eye diagram analysis with pass/fail masks for PCI Express, USB, SATA and other communications standards. | Enhances the debug experience unlike other BERT's by providing a familiar eye diagram of the test results to compare against a standards specific mask. |
| Error Location and BER contour analysis on PRBS 31 and other digital signals up to 28.6 Gb/sec. | Provides a quick understanding of signal integrity in terms of BER. Error location provides detailed BER pattern sensitivities to speed up identification of deterministic vs. random BER errors. |
| Optional Jitter Map provides fast jitter decomposition, accurate stress calibration at the DUT input. | Fast, effective method for determining long pattern PRBS31 jitter composition with triangulation. Graphical representation makes jitter analysis more thorough, yet simpler to follow. |
| Optional Digital Pre-emphasis Processor provides user controlled pre-emphasis on pattern generator supplied data. | Enables testing with compliant signals for standards like OIF-CEI3.0, Infiniband EDR, PCI Express, 10GBASE-KR, SATA, 40GBASE-KR4, 100GBASE-CAUI. |
| Optional Clock Recovery Units provide clock recovery up to 28.6 Gb/s. | Enables compliant testing and accurate Eye Pattern Analysis for high-speed serial and communication system standards. |
